In the last post, we saw that one of the major failings of the signed magnitude representation was that addition and subtraction could not be performed on the same hardware as for unsigned integers. As I pointed out, the reason for this is because negating a number in signed magnitude does not yield the additive inverse of that number. The ones complement representation eliminates this issue, although it does introduce new, subtle issues, and [spoiler] doesn’t address the problem of having two representations for zero.

I previously discussed the signed magnitude solution to representing signed integers as binary strings and pointed out that while it had the advantage of being simple, it also has some disadvantages. For starters, N-bit signed magnitude integers have two representations for zero: positive zero (a bitstring with N zeros) and negative zero (a bitstring with a one followed by N-1 zeros).

There is another significant disadvantage that isn’t obvious until you try to implement signed magnitude representation in silicon. Specifically, you can’t do mathematics with signed magnitude integers using the same hardware as is used for unsigned integers.

We humans and our meat computers don’t have any trouble recognizing the sign of a number. If there is a minus sign, “-,” in front of a number, that number is negative. If a number is prefixed by a plus sign, “+,” or, the more likely case, has no prefix at all, then the number is positive.

Computers of the silicon kind don’t have it so easy. They don’t have the luxury of pluses and minuses to tell them the sign of a number. All they have are zeros and ones, the alphabet of binary systems. So what is their solution?